Packages

c

tensil.zynq.tcu

AXIWrapperTCU

class AXIWrapperTCU[T <: Data with Num[T]] extends MultiIOModule

Linear Supertypes
MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. AXIWrapperTCU
  2. MultiIOModule
  3. RawModule
  4. BaseModule
  5. HasId
  6. InstanceId
  7. AnyRef
  8. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new AXIWrapperTCU(gen: T, layout: InstructionLayout, options: AXIWrapperTCUOptions)(implicit platformConfig: PlatformConfig)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. val boundary: Int
  10. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  11. final val clock: Clock
    Definition Classes
    MultiIOModule
  12. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  13. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  14. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  15. def desiredName: String
    Definition Classes
    BaseModule
  16. val dram0: Master
  17. val dram0BoundarySplitter: MemBoundarySplitter
  18. val dram0Converter: Converter[T]
  19. val dram1: Master
  20. val dram1BoundarySplitter: MemBoundarySplitter
  21. val dram1Converter: Converter[T]
  22. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  23. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  24. val error: Bool
  25. val gen: T
  26. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  27. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  28. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  29. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  30. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  31. def hasSeed: Boolean
    Definition Classes
    HasId
  32. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  33. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  34. val instruction: DecoupledIO[Instruction]
  35. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  36. val layout: InstructionLayout
  37. val maxLen: Int
  38. final lazy val name: String
    Definition Classes
    BaseModule
  39. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  40. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  41. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  42. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  43. val numScalarsPerWord: Int
  44. val options: AXIWrapperTCUOptions
  45. def parentModName: String
    Definition Classes
    HasId → InstanceId
  46. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  47. def pathName: String
    Definition Classes
    HasId → InstanceId
  48. implicit val platformConfig: PlatformConfig
  49. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  50. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  51. final val reset: Reset
    Definition Classes
    MultiIOModule
  52. val sample: DecoupledIO[WithLast[Sample]]
  53. val status: DecoupledIO[WithLast[Instruction]]
  54. def suggestName(seed: ⇒ String): AXIWrapperTCU.this.type
    Definition Classes
    HasId
  55. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  56. val tcu: TCU[T]
  57. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  58. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  59. def toString(): String
    Definition Classes
    AnyRef → Any
  60. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  61. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  62. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  63. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped