c

tensil.axi

MemBoundarySplitter

class MemBoundarySplitter extends Module

MemBoundarySplitter splits AXI requests up so that they do not cross memory boundaries. In the AXI spec, it is required that burst requests do not cross 4KB memory boundaries as this can cause the request to be sent to more than one slave. This module guarantees that requirement.

Note: We assume that the address is always aligned to the beat size. In other words, we don't support unaligned transfers.

Linear Supertypes
LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. MemBoundarySplitter
  2. LegacyModule
  3. MultiIOModule
  4. RawModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new MemBoundarySplitter(config: Config, boundary: Int, maxLen: Int)

    config

    the AXI configuration

    boundary

    the memory boundary size, usually 4K = 4096

    maxLen

    the maximum length of AXI burst transfers, usually 256

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. val bytesPerWord: Int
  11. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  12. final val clock: Clock
    Definition Classes
    MultiIOModule
  13. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  14. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  15. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  16. def desiredName: String
    Definition Classes
    BaseModule
  17. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  18. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  19. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  20. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  21. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  22. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  23. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  24. def hasSeed: Boolean
    Definition Classes
    HasId
  25. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  26. def illegal(address: UInt, length: UInt): Bool
  27. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  28. val io: Bundle { ... /* 2 definitions in type refinement */ }
    Definition Classes
    MemBoundarySplitter → LegacyModule
  29. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  30. def min(a: UInt, b: UInt): UInt
  31. final lazy val name: String
    Definition Classes
    BaseModule
  32. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  33. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  34. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  35. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  36. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  37. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  38. def parentModName: String
    Definition Classes
    HasId → InstanceId
  39. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  40. def pathName: String
    Definition Classes
    HasId → InstanceId
  41. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  42. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  43. val readAddressCounter: UInt
  44. val readDataQueue: chisel3.util.Queue[UInt]
  45. val readEnqueuer: MultiEnqueue
  46. val readLenCounter: UInt
  47. val readMerger: BurstSplitter[ReadData]
  48. final val reset: Reset
    Definition Classes
    MultiIOModule
  49. def suggestName(seed: ⇒ String): MemBoundarySplitter.this.type
    Definition Classes
    HasId
  50. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  51. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  52. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  53. def toString(): String
    Definition Classes
    AnyRef → Any
  54. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  55. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  56. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  57. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  58. val writeAddressCounter: UInt
  59. val writeDataQueue: chisel3.util.Queue[UInt]
  60. val writeEnqueuer: MultiEnqueue
  61. val writeLenCounter: UInt
  62. val writeResponseFilter: Filter[WriteResponse]
  63. val writeResponseQueue: chisel3.util.Queue[Bool]
  64. val writeSplitter: BurstSplitter[WriteData]

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped