c

tensil.mem

DualPortMem

class DualPortMem[T <: Data] extends Module

Linear Supertypes
LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. DualPortMem
  2. LegacyModule
  3. MultiIOModule
  4. RawModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new DualPortMem(gen: T, depth: Long, debug: Boolean = false, name: String = "mem")(implicit platformConfig: PlatformConfig)

Type Members

  1. class InnerDualPortMem[T <: Data] extends Module

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  9. val addressType: UInt
  10. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  11. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  12. final val clock: Clock
    Definition Classes
    MultiIOModule
  13. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  14. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  15. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  16. def connectPort(port: Port[T], inner: InnerPort[T], portName: String): Unit
  17. val depth: Long
  18. def desiredName: String
    Definition Classes
    BaseModule
  19. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  20. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  21. val gen: T
  22. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  23. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  24. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  25. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  26. lazy val getPorts: Seq[chisel3.internal.firrtl.Port]
    Definition Classes
    RawModule
  27. def hasSeed: Boolean
    Definition Classes
    HasId
  28. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  29. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  30. val io: Bundle { ... /* 4 definitions in type refinement */ }
    Definition Classes
    DualPortMem → LegacyModule
  31. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  32. val mem: InnerDualPortMem[T]
  33. final lazy val name: String
    Definition Classes
    BaseModule
  34. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  35. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  36. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  37. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  38. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  39. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  40. def parentModName: String
    Definition Classes
    HasId → InstanceId
  41. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  42. def pathName: String
    Definition Classes
    HasId → InstanceId
  43. implicit val platformConfig: PlatformConfig
  44. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  45. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  46. final val reset: Reset
    Definition Classes
    MultiIOModule
  47. def suggestName(seed: ⇒ String): DualPortMem.this.type
    Definition Classes
    HasId
  48. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  49. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  50. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  51. def toString(): String
    Definition Classes
    AnyRef → Any
  52. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  53. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  54. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  55. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped